Generally, flash memory devices are advantageous in that stored data is not lost even when its power supply is stopped. For this reason, flash memory devices are widely used for data storage of a PC BIOS, a set-top box, a printer and a network server. Recently, flash memory devices have also been used in digital cameras and mobile phones.
Among the different types of flash memory devices, an EEPROM (Electrically Erasable Programmable Read-Only Memory) type flash memory device may completely erase data from memory cells, or may erase data from memory cells by each unit sector.
In such an EEPROM type flash memory device, when in a programming mode, a channel hot electron is generated at a drain side, and the channel hot electron is stored in a floating gate, whereby a threshold voltage of the cell transistor increases.
Alternatively, when in an erasing mode of this EEPROM type flash memory device, a high voltage is generated between the floating gate and source/substrate, and the channel hot electron stored in the floating gate is discharged, thereby lowering the threshold voltage of the cell transistor.
The EEPROM type flash memory device may have an ETOX (EPROM Thin Oxide) cell or a split gate type cell. At this time, the ETOX cell is formed as a simple stack structure. In case of the split gate type cell, two transistors are formed in each cell. Specifically, in case of the ETOX cell, one memory cell has the stack structure of a floating gate and a control gate, wherein the floating gate stores charges therein, and the control gate receives a driving power.
Meanwhile, the split gate type cell is comprised of the two transistors, that is, a selection transistor and a cell transistor. Both the selection and cell transistors use one control gate, wherein some of the control gate is overlapped with the floating gate and the other is positioned in parallel to the surface of substrate.
Example FIGS. 1A to 1F are cross section views to illustrate a method of fabricating a self-alignment STI and a floating gate in a flash memory, which illustrate an ETOX cell-structure flash memory.
First, as shown in example FIG. 1A, a tunnel oxide film 2 is formed on an active area of a semiconductor substrate 1, and a first polysilicon film 3 for a floating gate is formed on the tunnel oxide film 2. After that, a nitride film (or oxide film) 4 is formed on the first polysilicon film 3, wherein the nitride film 4 functions as a hard mask. Then, a photoresist 5 which serves as a mask is formed on the nitride film 4.
Referring to example FIG. 1B, a STI (Shallow Trench Isolation) 6 is formed by using the photoresist 5 as the mask.
As shown in example FIG. 1C, the STI 6 is gap-filled with an insulation material, thereby forming an insulation film 7. After that, a first floating gate is formed by removing the nitride film 4 of the hard mask.
Thereon, a second polysilicon film 8 for a second floating gate is formed as shown in example FIG. 1D, and a photoresist mask 9 is formed on the second polysilicon film 8.
After that, the second polysilicon film 8 is etched by using the photoresist mask 9, to thereby form a second floating gate 10 as shown in example FIG. 1E.
As shown in example FIG. 1F, an ONO film 11 is formed on the second floating gate 10, and a control gate 12 is formed on the ONO film 11. Through these steps, a gate stack is completed.
However, when forming the floating gate of the device having the aforementioned self-alignment STI, it is impossible to realize a large coupling ratio (CR) with the first polysilicon film 3 used when forming the STI. Accordingly, use of the second polysilicon film 8 is required to form the floating gate. That is, there is a requirement for the additional mask to form the floating gate, whereby the fabrication cost and complexity increase. Furthermore, as design sizes are reduced it may be physically impossible to achieve the necessary overlay margins between the films.